Integrated circuits (ICs) are typically formed by doping different regions of a semiconductor substrate with n-type and/or p-type conductivity impurities. Complementary metal-oxide-semiconductor (CMOS) ICs may include n-channel MOS field effect transistors (MOSFETs) formed in p-type regions of a substrate as well as p-channel MOSFETs formed in n-type regions of the same substrate. In one example of a single well CMOS process, n-type wells (n-wells) may be formed in a p-type substrate. N-channel MOSFETs may be formed in the p-type regions, and p-channel MOSFETs may be formed in the n-wells. In many applications, n-wells are biased to a high power supply (e.g., VCC or VDD), while p-wells are biased to a low power supply reference (e.g., VSS or ground).
In some memory devices, such as dynamic random access memories (DRAMs), a substrate may be p-type, with n-wells formed therein. In addition, one or more array p-wells may be formed within n-wells. Such array p-wells may contain DRAM memory cells. While the p-type substrate may be biased to ground, the memory cell p-well may be biased to a negative voltage (sometimes called a back bias voltage, or VBB). A back bias voltage can reduce leakage from n-channel MOSFETs within such memory cells.